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| PRELIMINARY CY7C1371D CY7C1373D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Features * No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles * Can support up to 133-MHz bus operations with zero wait states -- Data is transferred on every clock * Pin-compatible and functionally equivalent to ZBTTM devices * Internally self-timed output buffer control to eliminate the need to use OE * Registered inputs for flow-through operation * Byte Write capability * 3.3V/2.5V I/O power supply * Fast clock-to-output times -- 6.5 ns (for 133-MHz device) -- 8.5 ns (for 100-MHz device) * Clock Enable (CEN) pin to enable clock and suspend operation * Synchronous self-timed writes * Asynchronous Output Enable * Offered in JEDEC-standard lead-free 100 TQFP, 119-ball BGA and 165-ball fBGA packages * Three chip enables for simple depth expansion * Automatic Power-down feature available using ZZ mode or CE deselect * JTAG boundary scan for BGA and fBGA packages * Burst Capability--linear or interleaved burst order * Low standby power Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Selection Guide 133 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 210 70 100 MHz 8.5 175 70 Unit ns mA mA Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05556 Rev. *A * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised November 3, 2004 PRELIMINARY 1 CY7C1371D CY7C1373D Logic Block Diagram - CY7C1371D (512K x 36) A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER A1 D1 A0 D0 Q1 A1' A0' Q0 BURST LOGIC ADV/LD BWA BWB BWC BWD WE WRITEREGISTRY ANDDATACOHERENCY CONTROLLOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S D A T A S T E E R I N G O U T P U T B U F F E R S E DQs DQPA DQPB DQPC DQPD OE CE1 CE2 CE3 ZZ INPUT E REGISTER READLOGIC SLEEP CONTROL 2 Logic Block Diagram - CY7C1373D (1 Mbit x 18) A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER A1 D1 A0 D0 Q1 A1' A0' Q0 BURST LOGIC ADV/LD BWA BWB WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S D A T A S T E E R I N G O U T P U T B U F F E R S E DQs DQPA DQPB WE OE CE1 CE2 CE3 ZZ INPUT E REGISTER READ LOGIC SLEEP CONTROL Document #: 38-05556 Rev. *A Page 2 of 30 PRELIMINARY Pin Configurations 100-lead TQFP BWD BWC BWB BWA CEN CLK ADV/LD CY7C1371D CY7C1373D CE1 CE2 CE3 VDD VSS WE OE A 82 A 100 A 99 A 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 A BYTE C BYTE D DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 81 A CY7C1371D 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50 DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA BYTE B BYTE A 39 40 41 42 NC / 72M A1 A0 VSS MODE NC / 288M NC / 144M VDD A A A A NC / 36M 43 A A A Document #: 38-05556 Rev. *A A A A A Page 3 of 30 PRELIMINARY Pin Configurations (continued) 100-lead TQFP BWB BWA CEN CLK ADV/LD CY7C1371D CY7C1373D CE1 CE2 CE3 VDD VSS WE OE NC NC A 82 100 A 99 A 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 A 83 A NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC BYTE B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 81 A CY7C1373D 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50 A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC BYTE A 39 40 41 42 NC / 72M A1 A0 VSS MODE NC / 288M NC / 144M VDD A A A A NC / 36M 43 A A A Document #: 38-05556 Rev. *A A A A A Page 4 of 30 PRELIMINARY Pin Configurations (continued) 119-ball BGA (3 Chip Enables with JTAG) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A CE2 A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC / 72M TMS CY7C1371D (512K x 36) 3 4 5 A A A A A VSS VSS VSS BWC VSS NC VSS BWD VSS VSS VSS MODE A TDI ADV/LD VDD NC CE1 OE A WE VDD CLK NC CEN A1 A0 VDD A TCK A A VSS VSS VSS BWB VSS NC VSS BWA VSS VSS VSS NC A TDO 6 A CE3 A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC / 36M NC 7 VDDQ NC NC DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ CY7C1371D CY7C1373D CY7C1373D (1 Mbit x 18) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC NC NC / 72M VDDQ 2 A CE2 A NC DQB NC DQB NC VDD DQB NC DQB NC DQPB A A TMS 3 A A A VSS VSS VSS BWB VSS NC VSS NC VSS VSS VSS MODE A TDI 4 A ADV/LD VDD NC CE1 OE A WE VDD CLK NC CEN A1 A0 VDD NC / 36M TCK 5 A A A VSS VSS VSS NC VSS NC VSS BWA VSS VSS VSS NC A TDO 6 A CE3 A DQPA NC DQA NC DQA VDD NC DQA NC DQA NC A A NC 7 VDDQ NC NC NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC ZZ VDDQ Document #: 38-05556 Rev. *A Page 5 of 30 PRELIMINARY Pin Configurations (continued) 165-ball fBGA (3 Chip enable with JTAG) CY7C1371D (512K x 36) CY7C1371D CY7C1373D 1 A B C D E F G H J K L M N P R NC / 288M NC DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE 2 A A NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC NC / 72M NC / 36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 CEN WE 8 ADV/LD OE 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A 11 NC NC / 144M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA NC A A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A A CY7C1373D (1 Mbit x 18) 1 A B C D E F G H J K L M N P R NC / 288M NC NC NC NC NC NC NC DQB DQB DQB DQB DQPB NC MODE 2 A A NC DQB DQB DQB DQB NC NC NC NC NC NC NC / 72M NC / 36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 CEN WE 8 ADV/LD OE 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A 11 A NC / 144M DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC NC A A NC NC NC NC NC NC DQA DQA DQA DQA NC A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A A Document #: 38-05556 Rev. *A Page 6 of 30 PRELIMINARY CY7C1371D CY7C1373D Pin Definitions Name A0, A1, A BWA, BWB BWC, BWD WE ADV/LD I/O InputSynchronous InputSynchronous InputSynchronous InputSynchronous Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter. Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. ZZ "Sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition with data integrity preserved. During normal operation, this pin can be connected to VSS or left floating. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D] are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. Power supply inputs to the core of the device. Power supply for the I/O circuitry. Ground for the device. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages. CLK CE1 CE2 CE3 OE InputClock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous CEN InputSynchronous ZZ InputAsynchronous I/OSynchronous DQs DQPX MODE I/OSynchronous Input Strap Pin VDD VDDQ VSS TDO Power Supply I/O Power Supply Ground JTAG serial output Synchronous Document #: 38-05556 Rev. *A Page 7 of 30 PRELIMINARY Pin Definitions (continued) Name TDI I/O JTAG serial input Synchronous JTAG serial input Synchronous JTAGClock - Description CY7C1371D CY7C1373D Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die. 36 Mbit, 72 Mbit, 144 Mbit and 288 Mbit are address expansion pins and are not internally connected to the die. Burst Read Accesses The CY7C1371D/CY7C1373D has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enable inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to the address bus is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQPX. On the next clock rise the data presented to DQs and DQPX (or a subset for byte write operations, see truth table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by BWX signals. The CY7C1371D/CY7C1373D provides byte write capability that is described in the truth table. Asserting the Write Enable input (WE) with the selected Byte Write Select input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1371D/CY7C1373D is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQPX inputs. Page 8 of 30 TMS TCK NC Functional Overview The CY7C1371D/CY7C1373D is a synchronous flow-through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BWX can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output will be tri-stated immediately. Document #: 38-05556 Rev. *A PRELIMINARY Doing so will tri-state the output drivers. As a safety precaution, DQs and DQPX are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1371D/CY7C1373D has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWX inputs must be driven in each cycle of the burst write, in order to write the correct bytes of data. CY7C1371D CY7C1373D Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10 Linear Burst Address Table (MODE = GND) First Address A1: A0 00 01 10 11 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 80 2tCYC Unit mA ns ns ns ns Truth Table [ 2, 3, 4, 5, 6, 7, 8] Operation Deselect Cycle Deselect Cycle Deselect Cycle Continue Deselect Cycle Read Cycle (Begin Burst) Read Cycle (Continue Burst) Dummy Read (Continue Burst) Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX None H X X L L X X None None None External Next Next X X X L X L X X L X H X H X H X X L X L X L L L L L L L L L H L H L H X X X H X H X X X X X X X X OE X X X X L L H H CEN L L L L L L L L CLK L->H L->H L->H L->H DQ Tri-State Tri-State Tri-State Tri-State L->H Data Out (Q) L->H Data Out (Q) L->H L->H Tri-State Tri-State NOP/Dummy Read (Begin Burst) External Notes: 2. X = "Don't Care." H = Logic HIGH, L = Logic LOW. BWX = 0 signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired byte write selects are asserted, see truth table for details. 3. Write is defined by BWX, and WE. See truth table for Read/Write. 4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes. 5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CEN = H, inserts wait states. 7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active. Document #: 38-05556 Rev. *A Page 9 of 30 PRELIMINARY Truth Table (continued)[ 2, 3, 4, 5, 6, 7, 8] Operation Write Cycle (Begin Burst) Write Cycle (Continue Burst) NOP/Write Abort (Begin Burst) Write Abort (Continue Burst) Ignore Clock Edge (Stall) Sleep Mode Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX External Next None Next Current None L X L X X X H X H X X X L X L X X X L L L L L H L H L H X X L X L X X X L L H H X X OE X X X X X X CEN L L L L H X CY7C1371D CY7C1373D CLK DQ L->H Data In (D) L->H Data In (D) L->H L->H L->H X Tri-State Tri-State - Tri-State Partial Truth Table for Read/Write[2, 3, 9] Function (CY7C1371D) Read Write No bytes written Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write Byte C - (DQC and DQPC) Write Byte D - (DQD and DQPD) Write All Bytes WE H L L L L L L BWA X H L H H H L BWB X H H L H H L BWC X H H H L H L BWD X H H H H L L Partial Truth Table for Read/Write[2, 3,9] Function (CY7C1373D) Read Write - No bytes written Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write All Bytes WE H L L L L BWA X H H H L BWB X H H H L IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1371D/CY7C1373D incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn't have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAPoperates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1371D/CY7C1373D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Note: 9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active. Document #: 38-05556 Rev. *A Page 10 of 30 PRELIMINARY TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1 CY7C1371D CY7C1373D TAP Controller Block Diagram 0 Bypass Register 210 TDI Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 Selection Circuitry TDO Identification Register x. . . . .210 Boundary Scan Register TCK TMS TAP CONTROLLER Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see figure. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) Document #: 38-05556 Rev. *A Page 11 of 30 PRELIMINARY state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows CY7C1371D CY7C1373D the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required--that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document #: 38-05556 Rev. *A Page 12 of 30 PRELIMINARY TAP Timing 1 Test Clock (TCK) t TMSS CY7C1371D CY7C1373D 4 5 6 2 3 t TH t TMSH t TL t CYC Test Mode Select (TMS) t TDIS t TDIH Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON'T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Parameter Clock tTCYC tTF tTH tTL tTDOV tTDOX tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise Description Range[10, 11] Min. 50 20 25 25 5 0 5 5 5 5 5 5 ns ns ns Max. Unit ns MHz ns ns ns ns ns ns Output Times Set-up Times Notes: 10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document #: 38-05556 Rev. *A Page 13 of 30 PRELIMINARY 3.3V TAP AC Test Conditions Input pulse levels ............................................... .VSS to 3.3V Input rise and fall times ................................................... 1 ns Input timing reference levels ...........................................1.5V Output reference levels...................................................1.5V Test load termination supply voltage...............................1.5V CY7C1371D CY7C1373D 2.5V TAP AC Test Conditions Input pulse levels................................................. VSS to 2.5V Input rise and fall time .....................................................1 ns Input timing reference levels........................................ .1.25V Output reference levels ................................................ 1.25V Test load termination supply voltage ............................ 1.25V 3.3V TAP AC Output Load Equivalent 1.5V 50 TDO Z O= 50 20pF 2.5V TAP AC Output Load Equivalent 1.25V 50 TDO Z O= 50 20pF TAP DC Electrical Characteristics And Operating Conditions (0C < TA < +70C; VDD = 3.3V 0.165V unless otherwise noted)[12] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VIN < VDDQ Description IOH = -4.0 mA IOH = -1.0 mA IOH = -100 A IOL = 8.0 mA IOL = 1.0 mA IOL = 100 A Conditions VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V Note: 12. All voltages referenced to VSS (GND). Min. 2.4 2.0 2.9 2.1 Max. Unit V V V V 0.4 0.4 0.2 0.2 2.0 1.7 -0.5 -0.3 -5 VDD + 0.3 VDD + 0.3 0.7 0.7 5 V V V V V V V V A Document #: 38-05556 Rev. *A Page 14 of 30 PRELIMINARY Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24) Device Width (23:18) Cypress Device ID (17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) CY7C1371D (512KX36) 000 01011 001001 100101 00000110100 1 CY7C1373D (1 MbitX18) 000 01011 001001 010101 00000110100 1 CY7C1371D CY7C1373D Description Describes the version number Reserved for internal use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor Indicates the presence of an ID register Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Order (119-ball BGA package) Boundary Scan Order (165-ball fBGA package) Bit Size (x36) 3 1 32 85 89 Bit Size (x18) 3 1 32 85 89 Identification Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05556 Rev. *A Page 15 of 30 PRELIMINARY 119-ball BGA Boundary Scan[13, 14] CY7C1371D (1 Mbit x 36) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Ball ID H4 T4 T5 T6 R5 L5 R6 U6 R7 T7 P6 N7 M6 L7 K6 P7 N6 L6 K7 J5 H6 G7 F6 E7 D7 H7 G6 E6 D6 C7 B7 C6 A6 C5 B5 G5 Bit # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Ball ID B6 D4 B4 F4 M4 A5 K4 E4 G4 A4 G3 C3 B2 B3 A3 C2 A2 B1 C1 D2 E1 F2 G1 H2 D1 E2 G2 H1 J3 2K L1 M2 N1 P1 K1 L2 CY7C1371D CY7C1373D CY7C1371D (1 Mbit x 36) Bit # 73 74 75 76 77 78 79 80 81 82 83 84 85 Ball ID N2 P2 R3 T1 R1 T2 L3 R2 T3 L4 N4 P4 Internal Notes: 13. Balls which are NC (No Connect) are pre-set LOW 14. Bit# 85 is pre-set HIGH Document #: 38-05556 Rev. *A Page 16 of 30 PRELIMINARY 119-ball BGA Boundary Scan Order[13, 14] CY7C1373D (2M x 18) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Ball ID H4 T4 T5 T6 R5 L5 R6 U6 R7 T7 P6 N7 M6 L7 K6 P7 N6 L6 K7 J5 H6 G7 F6 E7 D7 H7 G6 E6 D6 C7 B7 C6 A6 C5 B5 G5 Bit # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Ball ID B6 D4 B4 F4 M4 A5 K4 E4 G4 A4 G3 C3 B2 B3 A3 C2 A2 B1 C1 D2 E1 F2 G1 H2 D1 E2 G2 H1 J3 2K L1 M2 N1 P1 K1 L2 CY7C1371D CY7C1373D CY7C1373D (2M x 18) Bit # 73 74 75 76 77 78 79 80 81 82 83 84 85 Ball ID N2 P2 R3 T1 R1 T2 L3 R2 T3 L4 N4 P4 Internal Document #: 38-05556 Rev. *A Page 17 of 30 PRELIMINARY 165-ball fBGA Boundary Scan Order[13, 15] CY7C1371D (1 Mbit x 36) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Note: 15. Bit# 89 is Pre-set HIGH. CY7C1371D CY7C1373D CY7C1371D (1 Mbit x 36) Ball ID A9 B9 C10 A8 B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 Bit # 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Ball ID K2 L2 M2 N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal Ball ID N6 N7 10N P11 P8 R8 R9 P9 P10 R10 R11 H11 N11 M11 L11 K11 J11 M10 L10 K10 J10 H9 H10 G11 F11 E11 D11 G10 F10 E10 D10 C11 A11 B11 A10 B10 Bit # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Document #: 38-05556 Rev. *A Page 18 of 30 PRELIMINARY 165-ball fBGA Boundary Scan Order[13, 15] CY7C1373D (2M x 18) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Ball ID N6 N7 10N P11 P8 R8 R9 P9 P10 R10 R11 H11 N11 M11 L11 K11 J11 M10 L10 K10 J10 H9 H10 G11 F11 E11 D11 G10 F10 E10 D10 C11 A11 B11 A10 B10 Bit # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Ball ID A9 B9 C10 A8 B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 CY7C1371D CY7C1373D CY7C1373D (2M x 18) Bit # 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Ball ID K2 L2 M2 N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal Document #: 38-05556 Rev. *A Page 19 of 30 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V DC Voltage Applied to Outputs in Tri-State........................................... -0.5V to VDDQ + 0.5V DC Input Voltage....................................-0.5V to VDD + 0.5V CY7C1371D CY7C1373D Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Ambient Range Temperature VDD VDDQ Commercial 0C to +70C 3.3V - 5%/+10% 2.5V - 5% to VDD Industrial -40C to +85C Electrical Characteristics Over the Operating Range[16, 17] Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[16] Input LOW Voltage[16] Input Load Test Conditions VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V, VDD = Min., IOH = -4.0 mA VDDQ = 2.5V, VDD = Min., IOH = -1.0 mA VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V GND VI VDDQ Input = VDD Input Current of ZZ IDD ISB1 ISB2 ISB3 ISB4 VDD Operating Supply Current Automatic CE Power-down Current--TTL Inputs Input = VSS Input = VDD VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC VDD = Max, Device Deselected, VIN VIH or VIN VIL f = fMAX, inputs switching 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz All speeds -30 5 210 175 140 120 70 Min. 3.135 3.135 2.375 2.4 2.0 Max. 3.6 VDD 2.625 Unit V V V V V V V V V V V A A 30 A A A mA mA mA mA mA 2.0 1.7 -0.3 -0.3 -5 -5 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Input Current of MODE Input = VSS Automatic CE VDD = Max, Device Deselected, Power-down VIN 0.3V or VIN > VDD - 0.3V, Current--CMOS Inputs f = 0, inputs static Automatic CE VDD = Max, Device Deselected, or 7.5-ns cycle, 133 MHz Power-down VIN 0.3V or VIN > VDDQ - 0.3V 10-ns cycle, 100 MHz Current--CMOS Inputs f = fMAX, inputs switching Automatic CE VDD = Max, Device Deselected, All Speeds Power-down VIN VDD - 0.3V or VIN 0.3V, f = Current--TTL Inputs 0, inputs static 130 110 80 mA mA mA Notes: 16. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 17. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD Document #: 38-05556 Rev. *A Page 20 of 30 PRELIMINARY Thermal Resistance[18] Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TQFP Package 31 6 BGA Package 45 7 CY7C1371D CY7C1373D fBGA Package 46 3 Unit C/W C/W Capacitance[18] Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V TQFP Package 5 5 5 BGA Package 8 8 8 fBGA Package 9 9 9 Unit pF pF pF AC Test Loads and Waveforms 3.3V I/O Test Load OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 R = 317 VDDQ 5 pF GND R = 351 10% ALL INPUT PULSES 90% 90% 10% 1ns VT = 1.5V 1ns (a) 2.5V I/O Test Load OUTPUT Z0 = 50 2.5V INCLUDING JIG AND SCOPE (b) (c) R = 1667 VDDQ 5 pF GND R = 1538 10% ALL INPUT PULSES 90% 90% 10% 1ns OUTPUT RL = 50 VT = 1.25V 1ns (a) INCLUDING JIG AND SCOPE (b) (c) Note: 18. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05556 Rev. *A Page 21 of 30 PRELIMINARY Switching Characteristics Over the Operating Range[23, 24] 133 MHz Parameter tPOWER Clock tCYC tCH tCL Output Times tCDV tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Setup Times tAS tALS tWES tCENS tDS tCES Hold Times tAH tALH tWEH tCENH tDH tCEH Address Hold After CLK Rise ADV/LD Hold After CLK Rise WE, BWX Hold After CLK Rise CEN Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Address Set-up Before CLK Rise ADV/LD Set-up Before CLK Rise WE, BWX Set-up Before CLK Rise CEN Set-up Before CLK Rise Data Input Set-up Before CLK Rise Chip Enable Set-Up Before CLK Rise 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z[20, 21, 22] Clock to High-Z[20, 21, 22] 0 4.0 OE LOW to Output Valid OE LOW to Output Low-Z[20, 21, 22] OE HIGH to Output High-Z[20, 21, 22] 2.0 2.0 4.0 3.2 0 6.5 2.0 2.0 Clock Cycle Time Clock HIGH Clock LOW 7.5 2.1 2.1 10 2.5 2.5 [19] CY7C1371D CY7C1373D 100 MHz Min. 1 Max. Unit ms ns ns ns 8.5 ns ns ns 5.0 3.8 5.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. 1 Max. Notes: 19. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 20. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 21. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 22. This parameter is sampled and not 100% tested. 23. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 24. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05556 Rev. *A Page 22 of 30 PRELIMINARY Switching Waveforms Read/Write Waveforms[25, 26, 27] CY7C1371D CY7C1373D 1 CLK tCENS tCENH 2 tCYC 3 4 5 6 7 8 9 10 tCH tCL CEN tCES tCEH CE ADV/LD WE BWX ADDRESS tAS A1 tAH A2 A3 tCDV tCLZ A4 tDOH Q(A3) Q(A4) tOEHZ tOEV A5 tCHZ A6 A7 DQ tDS D(A1) tDH D(A2) D(A2+1) Q(A4+1) D(A5) Q(A6) D(A7) OE COMMAND WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) tOELZ tDOH WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT DON'T CARE UNDEFINED Notes: 25. For this waveform ZZ is tied LOW. 26. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 27. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional. 3 Document #: 38-05556 Rev. *A Page 23 of 30 PRELIMINARY Switching Waveforms (continued) NOP, STALL AND DESELECT Cycles[25, 26, 28] CY7C1371D CY7C1373D 1 CLK tCENS tCENH 2 tCYC 3 4 5 6 7 8 9 10 tCH tCL CEN tCES tCEH CE ADV/LD WE BWX ADDRESS tAS A1 tAH A2 A3 tCDV tCLZ A4 tDOH Q(A3) Q(A4) tOEHZ tOEV A5 tCHZ A6 A7 DQ tDS D(A1) tDH D(A2) D(A2+1) Q(A4+1) D(A5) Q(A6) D(A7) OE COMMAND WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) tOELZ tDOH WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT DON'T CARE UNDEFINED Note: 28. The Ignore Clock Edge or Stall cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. Document #: 38-05556 Rev. *A Page 24 of 30 PRELIMINARY Switching Waveforms (continued) ZZ Mode Timing[29, 30] CLK t ZZ t ZZREC CY7C1371D CY7C1373D ZZ t ZZI I SUPPLY I DDZZ t RZZI DESELECT or READ Only ALL INPUTS (except ZZ) Outputs (Q) High-Z DON'T CARE Notes: 29. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 30. DQs are in high-Z when exiting ZZ sleep mode. 4 Document #: 38-05556 Rev. *A Page 25 of 30 PRELIMINARY Ordering Information Speed (MHz) 133 Ordering Code CY7C1371D-133AXC CY7C1373D-133AXC CY7C1371D-133AXI CY7C1373D-133AXI CY7C1371D-133BGC CY7C1373D-133BGC CY7C1371D-133BGI CY7C1373D-133BGI CY7C1371D-133BZC CY7C1373D-133BZC CY7C1371D-133BZI CY7C1373D-133BZI CY7C1371D-133BGXC CY7C1373D-133BGXC CY7C1371D-133BGXI CY7C1373D-133BGXI CY7C1371D-133BZXC CY7C1373D-133BZXC CY7C1371D-133BZXI CY7C1373D-133BZXI 100 CY7C1371D-100AXC CY7C1373D-100AXC CY7C1371D-100AXI CY7C1373D-100AXI CY7C1371D-100BGC CY7C1373D-100BGC CY7C1371D-100BGI ICY7C1373D-100BGI CY7C1371D-100BZC CY7C1373D-100BZC CY7C1371D-100BZI CY7C1373D-100BZI CY7C1371D-100BGXC CY7C1373D-100BGXC CY7C1371D-100BGXI ICY7C1373D-100BGXI CY7C1371D-100BZXC CY7C1373D-100BZXC CY7C1371D-100BZXI CY7C1373D-100BZXI BB165D BB165D BG119 BG119 BB165D BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG BG119 BG119 A101 A101 BB165D BB165D BG119 BG119 BB165D BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG BG119 A101 BG119 Package Name A101 Part and Package Type CY7C1371D CY7C1373D Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)3 Chip Enables and JTAG Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)3 Chip Enables and JTAG Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Lead-free BG packages (Ordering Code: BGX) will be available in 2005. Document #: 38-05556 Rev. *A Page 26 of 30 PRELIMINARY Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 16.000.20 14.000.10 100 1 81 80 CY7C1371D CY7C1373D DIMENSIONS ARE IN MILLIMETERS. 1.400.05 0.300.08 22.000.20 20.000.10 0.65 TYP. 30 31 50 51 121 (8X) SEE DETAIL A 0.20 MAX. 1.60 MAX. STAND-OFF 0.05 MIN. 0.15 MAX. 0.10 R 0.08 MIN. 0.20 MAX. 0 MIN. 0.25 GAUGE PLANE R 0.08 MIN. 0.20 MAX. SEATING PLANE 0-7 0.600.15 0.20 MIN. 1.00 REF. DETAIL A 51-85050-*A Document #: 38-05556 Rev. *A Page 27 of 30 PRELIMINARY Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 CY7C1371D CY7C1373D 51-85115-*B Document #: 38-05556 Rev. *A Page 28 of 30 PRELIMINARY Package Diagrams (continued) 165 FBGA 13 x 15 x 1.40 MM BB165D CY7C1371D CY7C1373D 51-85180-** NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05556 Rev. *A Page 29 of 30 (c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY Document History Page CY7C1371D CY7C1373D Document Title: CY7C1371D/CY7C1373D 18-Mbit (512K x 36/1 Mbit x 18) Flow-Through SRAM with NoBLTM Architecture Document Number: 38-05556 REV. ** *A ECN NO. 254513 288531 Issue Date See ECN See ECN Orig. of Change RKF SYT New data sheet Edited description under "IEEE 1149.1 Serial Boundary Scan (JTAG)" for non-compliance with 1149.1 Removed 117 Mhz Speed Bin Added lead-free information for 100-Pin TQFP , 119 BGA and 165 FBGA Packages Added comment of `Lead-free BG packages availability' below the Ordering Information Description of Change Document #: 38-05556 Rev. *A Page 30 of 30 |
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